An exit from the FPGA dead end

No benchmarks of our own here. Facts that have happened are linked. Forecasts and probabilities are our judgment, and we label them. We are optimistic about this direction, and we write down what would have to be true for it to hold.

The short answer

In September 2026, the Kirin 2026 shipped. It is the first SoC in volume production with logic folding, and after teardown the numbers are: density up from 155 to 238 MTr/mm² (+55%), and at equal performance, NPU power down 66% and the CPU prime core down 41%.

This is not a roadmap. It is a phone chip already in people's hands.

So the real question is not whether Huawei can do it. It is: can the same lever pull FPGA and CGRA out of a twenty-year dead end?

Our answer: it looks promising. Not because the numbers got bigger, but because it loosens three constraints at once — and those three are exactly where AI hurts most.

The dead end: what the FPGA is stuck on

The FPGA is not weak. Three structural problems keep it at glue and prototypes:

1. Area. Configuration SRAM and programmable switches eat a large share of the die. The same function is an order of magnitude bigger than in an ASIC.
2. The memory wall. Programmable fabric cannot reach HBM-class bandwidth, so it hangs off external DRAM. Once inference moves to large models, it loses on data movement first.
3. Staticity. Weights and routing are fixed at synthesis time. Change the model and you run the whole toolchain again. In an era when models are revised every quarter, that is the largest cost of all.

The third is discussed least, and it is where the FPGA should be winning in AI. The hardware just was never fast or cheap enough to change.

Folding hands over three keys

In 2026, logic folding means two different things, and they unlock different locks:

The three keys map onto the three problems:

• Density. Move configuration memory out of the logic layer (M3D FPGA, DAC 2025) and the area tax finally gets a discount.
• Bandwidth. Bond SRAM or DRAM on top. A 28nm 3D logic-on-SRAM CGRA has already shown 4TB/s of vertical bandwidth, on 51.19mm² at 1GHz and 0.9V.
• Reconfiguration speed. Hybrid bonding brings reprogramming latency below 10ns (vFPGA, 2026). Temporal folding becomes affordable for the first time.

One more: face-to-face bonding shortens wires. LaZagna (ICCAD 2025) measured up to 6.7% critical path reduction and 22.9% less wirelength in VTR simulation.

None of these is a revolution on its own. Together, they are the first chance in twenty years to push all three taxes down at the same time.

What has already happened, not what is forecast

Everything in this section is checkable. That matters, because it moves folding from papers to products.

Density and power. Against the previous planar Kirin 9030 Pro: +55% density, and at equal performance NPU power down 66% and the CPU prime core down 41%, with GPU figures reported between 45% and 58%. Huawei's explanation: most of a chip's energy goes into moving data along metal wires. Folding shortens those wires and cuts interconnect capacitance, so equal performance can be had at lower frequency and voltage.

More surgical than expected. Huawei calls it selective folding: only critical paths and critical timing get folded. Thermal-aware placement interleaves hot and cool circuits so hotspots do not stack vertically. Vertical interconnects already exceed 100 million, with a three-year target of 720nm top-metal pitch and over 200 million interconnects.

Process is no longer the excuse. SMIC's N+3 has entered 5nm-class volume production (TechPowerUp). Folding is not a substitute for missing process technology, then, but an architectural option worth taking even when the process is there. That changes the nature of the argument.

The official roadmap puts it in AI accelerators. Per the V2 Tau paper, Ascend 910C in 2025 and 950 in 2026 still use chiplets and 2.5D; around 2030, Ascend 990 brings logic folding into AI accelerators, and from then on 3D folding carries the main line.

Looking forward: what folding actually unlocks

If folding holds up, the FPGA's role in inference moves from glue to reconfigurable inference engine. Four things become practical:

One: continual learning. Weights and routing update with the data, without taping out for every model version. This is the ASIC's structural weakness: change the model and it is obsolete.

Two: dynamic routing. MoE expert routing is, at heart, "each token takes a different path". Making that reconfigurable in hardware is cheaper than simulating it with caches in software. Routing is what FPGAs and CGRAs already do.

Three: dynamic weights and precision. One chip can run INT4 today and FP8 tomorrow, or change where KV lives when the context gets long. GPUs schedule this in software; reconfigurable hardware can change the circuit.

Four: edge and field. Sites that cannot reach the network, cannot afford a loud fan, cannot risk a supply cut — they need something buyable, changeable and supported for ten years. GPUs cannot go there and ASIC volumes cannot sustain it.

Put those together and the conclusion is different from the usual one: the FPGA does not sell compute. It sells the ability to face uncertainty. And the next stretch of AI is full of it.

Careful, though: four things still missing

Optimism is not blindness. If these four are not solved, folding stays a nice prototype.

One: the 2026 implementation is conservative. Kirin uses micro-bumps and standard-pitch bonding, not the finest pitch, and TSV keep-out zones still displace standard cells. The real density dividend waits for finer pitch.

Two: the toolchain. 3D demands cross-die place-and-route, timing, thermal and signal-integrity signoff, with all stacked dies treated as one continuous design entity. For an FPGA that means rewriting the whole compile flow. This is harder than bonding wafers.

Three: heat and yield. Two active logic layers double power density. Huawei proved with a phone that "denser does not mean hotter", but FPGAs live in fanless, industrial and base-station environments where the test is ten-year reliability, not a benchmark.

Four: cost. Even HBM4 is still hesitating on hybrid bonding. Yields multiply, costs add, and nobody has said who pays the premium.

These are not reasons to dismiss it. They are the list of what "it works" would have to mean.

Checkpoints: what to watch over the next three years

The optimistic 2030 case

Decode speed follows one relation:

For a 7B model at INT4, batch 1, efficiency 0.6 (weights about 3.5 GB):

Four to 340 is 85×. That 85× crosses two product classes and is not a like-for-like comparison.

Against a GPU of the same year, the 3D FPGA is still about four times slower. But that comparison only decides the outcome for large models, batched, bandwidth-bound. For latency-sensitive, fragmented, tokens-per-watt-constrained work, the baseline changes and so does the answer.

Relative to a comparable 2026 FPGA, our estimate is:

Median around 15×, expectation around 22×. These numbers are more optimistic than our earlier version, because Kirin already delivered density and power at the same time. That was the hardest of the three keys.

Our read

These are judgments, not a model. Their common premise is that toolchains catch up with hardware by 2028. If they do not, everything above comes down.

Limits

We have no measurements. Every number comes from public reporting, papers or vendors; the Kirin power figures are Huawei's own measurements.

The optimism has a source, and a bias. Kirin is one data point, tuned under phone power budgets and selective folding. Move to a 600mm² FPGA and the heat and yield arithmetic has to be redone.

The probabilities are ours. No statistical model stands behind them. Treat them as a view.

The forecast rests on three assumptions. Hybrid bonding yield and cost land by 2030, 3D-aware toolchains mature, and 2030 GPUs do not improve faster than expected.

If you're placing a bet

Three questions beat memorising any number here. They are also the first three we ask in a proof of concept.

Will your model keep changing? If yes, reconfigurable value holds. If it is settled and volumes are large, tape out an ASIC.

Is your bottleneck bandwidth or latency? For large-model batched inference, bandwidth decides and the FPGA does not win. Latency, offline, tokens per watt — that is its ground.

Is your baseline a die or a board? If you compete against 2–4 discrete parts and a PCB, folding has an account to settle.

As for betting now: hardware bets are usually lost to being early, not to being late. But this one is worth putting on the 2027 options list.