[{"data":1,"prerenderedAt":2258},["ShallowReactive",2],{"post-logic-folding-fpga-cgra":3,"site-info":1674,"related-en-logic-folding-fpga-cgra":1770},{"zh":4,"en":893},{"id":5,"title":6,"author":7,"body":8,"cover":873,"coverAlt":874,"date":875,"description":876,"draft":877,"extension":878,"featured":877,"lang":879,"meta":880,"navigation":881,"ogImage":882,"path":883,"seo":884,"slug":885,"stem":886,"tags":887,"translationKey":885,"updated":891,"__hash__":892},"blog\u002Fblog\u002Fzh-TW\u002Flogic-folding-fpga-cgra.md","FPGA 的死胡同，邏輯折疊可能是出口","Jecision",{"type":9,"value":10,"toc":858},"minimark",[11,18,22,25,28,35,38,42,45,67,70,73,76,135,138,184,193,196,200,203,220,230,242,254,258,261,267,273,279,285,292,296,299,305,311,317,329,332,336,390,394,397,605,608,657,660,663,666,738,741,744,796,799,802,808,814,820,826,829,837,843,849,855],[12,13,14],"blockquote",{},[15,16,17],"p",{},"這篇沒有我們的實測。已發生的事實都有連結；預測與機率是我們的判斷，會標明。我們對這個方向是樂觀的，但會把「要看到什麼才算成立」寫清楚。",[19,20,21],"h2",{"id":21},"先講結論",[15,23,24],{},"2026 年 9 月，麒麟 2026 出貨。它是第一顆把邏輯折疊帶進量產的 SoC。拆機之後的數字是：密度從 1.55 億顆\u002Fmm² 升到 2.38 億（+55%），同效能下 NPU 功耗降 66%、CPU 大核降 41%。",[15,26,27],{},"這不是路線圖，是已經在手上的手機晶片。",[15,29,30,31],{},"所以真正的問題不是「華為行不行」。是：",[32,33,34],"strong",{},"同一個槓桿，能不能把 FPGA 與 CGRA 從二十年的死胡同裡拉出來？",[15,36,37],{},"我的答案：有望。但理由不是「數字變大」，而是它同時鬆開三個卡點，而這三個卡點剛好是 AI 時代最痛的地方。",[19,39,41],{"id":40},"死胡同fpga-卡在什麼地方","死胡同：FPGA 卡在什麼地方",[15,43,44],{},"FPGA 不是不強，是三個體質問題讓它一直停在「膠合與原型」：",[46,47,48,55,61],"ol",{},[49,50,51,54],"li",{},[32,52,53],{},"面積。"," 配置 SRAM 與可程式開關吃掉一大塊面積，同樣功能比 ASIC 大一個數量級。",[49,56,57,60],{},[32,58,59],{},"記憶體牆。"," 可程式織體換不到 HBM 級的頻寬，只能外掛 DRAM；推論一進入大模型，就先輸在搬資料。",[49,62,63,66],{},[32,64,65],{},"靜態性。"," 權重與路由在合成時就固定，模型一改就得重新走一次工具鏈。這件事在模型每季改版的年代，變成最大的成本。",[15,68,69],{},"第三點最少被討論，但它其實是 FPGA 在 AI 時代最應該贏的地方。只是過去的硬體做不到「改得夠快、改得夠便宜」。",[19,71,72],{"id":72},"折疊給了三把鑰匙",[15,74,75],{},"邏輯折疊在 2026 年指兩件不同的事，而它們解的是不同的鎖：",[77,78,79,92],"table",{},[80,81,82],"thead",{},[83,84,85,89],"tr",{},[86,87,88],"th",{},"華為 LogicFolding（折 Z 軸）",[86,90,91],{},"學術 temporal logic folding（折 T 軸）",[93,94,95,109,122],"tbody",{},[83,96,97,104],{},[98,99,100,103],"td",{},[32,101,102],{},"做法","：一個邏輯區塊拆成上下兩層、面對面鍵合",[98,105,106,108],{},[32,107,102],{},"：同一組 LUT 每隔幾個 cycle 重配置一次",[83,110,111,117],{},[98,112,113,116],{},[32,114,115],{},"解鎖","：密度、頻率、更短的路徑",[98,118,119,121],{},[32,120,115],{},"：用時間換面積，重配置變成常態",[83,123,124,130],{},[98,125,126,129],{},[32,127,128],{},"實證","：麒麟 2026（已量產）",[98,131,132,134],{},[32,133,128],{},"：NATURE／NanoMap、Tabula Spacetime",[15,136,137],{},"三把鑰匙分別對應三個卡點：",[139,140,141,155,172],"ul",{},[49,142,143,146,147,154],{},[32,144,145],{},"密度","：把配置記憶體搬出邏輯層（BEOL 配置記憶體，",[148,149,153],"a",{"href":150,"rel":151},"https:\u002F\u002Fdoi.org\u002F10.1109\u002FDAC63849.2025.11132615",[152],"nofollow","M3D FPGA，DAC 2025","），面積稅就有機會打折。",[49,156,157,160,161,166,167,171],{},[32,158,159],{},"頻寬","：把 SRAM 或 DRAM 貼上去。28nm 3D logic-on-SRAM CGRA 已經做出 ",[148,162,165],{"href":163,"rel":164},"https:\u002F\u002Fieeexplore.ieee.org\u002Fdocument\u002F11509617",[152],"4TB\u002Fs 垂直頻寬","，51.19mm²、",[148,168,170],{"href":169},"mailto:1GHz@0.9V","1GHz@0.9V","。",[49,173,174,177,178,183],{},[32,175,176],{},"重配置速度","：混合鍵合把重配置延遲壓到 sub-10ns（",[148,179,182],{"href":180,"rel":181},"https:\u002F\u002Fdoi.org\u002F10.1145\u002F3748173.3779206",[152],"vFPGA，2026","），時間折疊第一次在成本上說得通。",[15,185,186,187,192],{},"再加一項：面對面鍵合讓線變短。",[148,188,191],{"href":189,"rel":190},"https:\u002F\u002Farxiv.org\u002Fabs\u002F2505.05579",[152],"LaZagna（ICCAD 2025）","在 VTR 模擬裡量到臨界路徑最多縮短 6.7%、總線長 22.9%。",[15,194,195],{},"單看每一項都不算革命。放在一起，是 FPGA 二十年來第一次有機會把三個稅同時往下壓。",[19,197,199],{"id":198},"已經發生的事不是預測","已經發生的事，不是預測",[15,201,202],{},"這一節全部是可以查證的。它重要，因為它把「折疊」從論文搬到商品。",[15,204,205,208,209,171,214,219],{},[32,206,207],{},"密度與功耗。"," 麒麟 2026 對比前代平面架構的麒麟 9030 Pro：密度 +55%，同效能下 NPU 功耗 −66%、CPU 大核 −41%，",[148,210,213],{"href":211,"rel":212},"https:\u002F\u002Fwww.ithome.com\u002F0\u002F998\u002F598.htm",[152],"GPU 的數字各家報導落在 45–58%",[148,215,218],{"href":216,"rel":217},"https:\u002F\u002Fm.cena.com.cn\u002Fsemi\u002F20261021\u002F129796.html",[152],"華為的說法","是：晶片能耗大半花在金屬走線搬資料。折疊縮短路徑、降低互連電容，所以同效能可以用更低的頻率與電壓。",[15,221,222,225,226,171],{},[32,223,224],{},"做得比預期細。"," 華為強調這是「選擇性折疊」：只折關鍵路徑與關鍵時序。再配合熱感知布局，讓冷熱電路交錯、避免熱點垂直重疊。垂直互連已經超過 1 億根，",[148,227,229],{"href":211,"rel":228},[152],"目標三年內做到 720nm 頂層金屬節距、2 億根以上",[15,231,232,235,236,241],{},[32,233,234],{},"製程也不再是藉口。"," SMIC 的 N+3 已經進入 5nm 級量產（",[148,237,240],{"href":238,"rel":239},"https:\u002F\u002Fwww.techpowerup.com\u002F344000\u002Fchinese-smic-achieves-5-nm-production-on-n-3-node-without-euv-tools",[152],"TechPowerUp","）。也就是說，折疊不是在「沒有先進製程」時的替代品，而是「有製程之後仍然值得做」的架構選項。這一點改變了整件事的性質。",[15,243,244,247,248,253],{},[32,245,246],{},"官方路線圖把它排進 AI 加速器。"," 依韜定律論文 V2，2025 年的昇騰 910C、2026 年的 950 仍用 Chiplet 與 2.5D；",[148,249,252],{"href":250,"rel":251},"https:\u002F\u002Fwww.trendforce.com\u002Fnews\u002F2026\u002F07\u002F06\u002Fnews-huawei-expands-tau-scaling-law-v2-paper-highlighting-logicfolding-path-to-ascend-ai-chips-around-2030\u002F",[152],"約 2030 年的昇騰 990 會把邏輯折疊引進 AI 加速器","，此後 3D 折疊成為主要載體。",[19,255,257],{"id":256},"往前看折疊真正解鎖的是什麼","往前看：折疊真正解鎖的是什麼",[15,259,260],{},"如果折疊成立，FPGA／CGRA 在 AI 推論的位置會從「膠合」變成「可重構的推理引擎」。有四件事會因此變得可行：",[15,262,263,266],{},[32,264,265],{},"一、持續學習。"," 權重與路由可以隨資料更新，不必為每一版模型重投片。ASIC 的結構弱點正好在這裡：模型一改，它就過期。",[15,268,269,272],{},[32,270,271],{},"二、動態路由。"," MoE 的 expert routing 本質上是「每個 token 走不同的路徑」。這件事在硬體層可變，比在軟體層用快取模擬更省。FPGA 與 CGRA 天生就在做路由。",[15,274,275,278],{},[32,276,277],{},"三、動態權重與精度。"," 同一顆晶片可以今天跑 INT4、明天跑 FP8，或在長上下文時切換 KV 的存放層級。GPU 靠軟體排程，可重構硬體可以直接改電路。",[15,280,281,284],{},[32,282,283],{},"四、邊緣與現場。"," 不能連網、不能大聲散熱、不能被斷料的場景，需要的是「買得到、改得動、十年供貨」。這一段 GPU 進不去，ASIC 的出貨量養不活。",[15,286,287,288,291],{},"把這四件事放在一起，就會看到一個和過去不同的結論：",[32,289,290],{},"FPGA 賣的不是算力，是面對不確定性的能力。"," 而 AI 的下一段，剛好充滿不確定性。",[19,293,295],{"id":294},"但要小心求證四個還沒到","但要小心求證：四個還沒到",[15,297,298],{},"樂觀不等於盲目。以下四件事如果沒解決，折疊就只是漂亮的原型：",[15,300,301,304],{},[32,302,303],{},"一、2026 的實作是保守版。"," 麒麟用的是微凸塊與標準間距鍵合，不是最細的間距；TSV 的禁置區還會吃掉標準元件的位置。真正的密度紅利要等間距往下走。",[15,306,307,310],{},[32,308,309],{},"二、工具鏈。"," 3D 要跨 die 做 P&R、時序、熱、SI 簽核，把多顆晶粒當成一個連續的設計實體。對 FPGA 來說，這等於整個編譯流程要重寫。這件事比晶圓鍵合難。",[15,312,313,316],{},[32,314,315],{},"三、散熱與良率。"," 兩層主動邏輯把功率密度翻倍。華為用手機證明「密度高不等於更熱」。但 FPGA 長期跑在無風扇、工業、基地台環境，考驗的是十年可靠度，不是跑分。",[15,318,319,322,323,328],{},[32,320,321],{},"四、成本。"," 混合鍵合連 HBM4 都還在",[148,324,327],{"href":325,"rel":326},"https:\u002F\u002Ftechnews.tw\u002Fai-agent\u002Fhuaweis-chip-law-looks-less-like-moore-and-more-like-marketing\u002F11265\u002F",[152],"觀望","。良率相乘、成本相加，誰來付溢價，目前沒有答案。",[15,330,331],{},"這四點不是反對理由，是「什麼時候知道它成立」的清單。",[19,333,335],{"id":334},"檢查點未來三年要看什麼","檢查點：未來三年要看什麼",[77,337,338,348],{},[80,339,340],{},[83,341,342,345],{},[86,343,344],{},"訊號",[86,346,347],{},"為什麼重要",[93,349,350,358,366,374,382],{},[83,351,352,355],{},[98,353,354],{},"鍵合節距往 720nm 以下走、互連數破 2 億",[98,356,357],{},"密度紅利能不能延續",[83,359,360,363],{},[98,361,362],{},"昇騰 990 如期在 2030 前導入折疊",[98,364,365],{},"AI 加速器真的採用，不只是手機",[83,367,368,371],{},[98,369,370],{},"出現第一顆商用的 3D logic-on-logic FPGA",[98,372,373],{},"從「華為的 SoC」變成「產業的選項」",[83,375,376,379],{},[98,377,378],{},"3D-aware 的 EDA 與編譯器能把利用率拉高",[98,380,381],{},"沒有工具鏈，硬體只是樣品",[83,383,384,387],{},[98,385,386],{},"邊緣裝置的 tokens\u002FJ 明顯優於 2026 年的 GPU",[98,388,389],{},"商業價值最終要落在每瓦推論",[19,391,393],{"id":392},"_2030-的樂觀情境","2030 的樂觀情境",[15,395,396],{},"推論速度的關係很簡單：",[398,399,402],"span",{"className":400},[401],"katex-display",[398,403,406,451],{"className":404},[405],"katex",[398,407,410],{"className":408},[409],"katex-mathml",[411,412,415],"math",{"xmlns":413,"display":414},"http:\u002F\u002Fwww.w3.org\u002F1998\u002FMath\u002FMathML","block",[416,417,418,446],"semantics",{},[419,420,421,425,429],"mrow",{},[422,423,424],"mtext",{},"tok\u002Fs",[426,427,428],"mo",{},"≈",[430,431,432,443],"mfrac",{},[419,433,434,437,440],{},[422,435,436],{},"記憶體頻寬",[426,438,439],{},"×",[422,441,442],{},"頻寬效率",[422,444,445],{},"每 token 要讀的權重",[447,448,450],"annotation",{"encoding":449},"application\u002Fx-tex","\\text{tok\u002Fs} \\approx \\frac{\\text{記憶體頻寬} \\times \\text{頻寬效率}}{\\text{每 token 要讀的權重}}",[398,452,456,485],{"className":453,"ariaHidden":455},[454],"katex-html","true",[398,457,460,465,473,478,482],{"className":458},[459],"base",[398,461],{"className":462,"style":464},[463],"strut","height:1em;vertical-align:-0.25em;",[398,466,470],{"className":467},[468,469],"mord","text",[398,471,424],{"className":472},[468],[398,474],{"className":475,"style":477},[476],"mspace","margin-right:0.2778em;",[398,479,428],{"className":480},[481],"mrel",[398,483],{"className":484,"style":477},[476],[398,486,488,492],{"className":487},[459],[398,489],{"className":490,"style":491},[463],"height:2.0463em;vertical-align:-0.686em;",[398,493,495,500,601],{"className":494},[468],[398,496],{"className":497},[498,499],"mopen","nulldelimiter",[398,501,503],{"className":502},[430],[398,504,508,592],{"className":505},[506,507],"vlist-t","vlist-t2",[398,509,512,587],{"className":510},[511],"vlist-r",[398,513,517,544,555],{"className":514,"style":516},[515],"vlist","height:1.3603em;",[398,518,520,525],{"style":519},"top:-2.314em;",[398,521],{"className":522,"style":524},[523],"pstrut","height:3em;",[398,526,528],{"className":527},[468],[398,529,531,536,540],{"className":530},[468,469],[398,532,535],{"className":533},[468,534],"cjk_fallback","每",[398,537,539],{"className":538},[468]," token ",[398,541,543],{"className":542},[468,534],"要讀的權重",[398,545,547,550],{"style":546},"top:-3.23em;",[398,548],{"className":549,"style":524},[523],[398,551],{"className":552,"style":554},[553],"frac-line","border-bottom-width:0.04em;",[398,556,558,561],{"style":557},"top:-3.677em;",[398,559],{"className":560,"style":524},[523],[398,562,564,570,574,578,581],{"className":563},[468],[398,565,567],{"className":566},[468,469],[398,568,436],{"className":569},[468,534],[398,571],{"className":572,"style":573},[476],"margin-right:0.2222em;",[398,575,439],{"className":576},[577],"mbin",[398,579],{"className":580,"style":573},[476],[398,582,584],{"className":583},[468,469],[398,585,442],{"className":586},[468,534],[398,588,591],{"className":589},[590],"vlist-s","​",[398,593,595],{"className":594},[511],[398,596,599],{"className":597,"style":598},[515],"height:0.686em;",[398,600],{},[398,602],{"className":603},[604,499],"mclose",[15,606,607],{},"以 7B 模型、INT4、batch 1、頻寬效率 0.6 估算（權重約 3.5 GB）：",[77,609,610,622],{},[80,611,612],{},[83,613,614,617,619],{},[86,615,616],{},"機器",[86,618,159],{},[86,620,621],{},"推論速度",[93,623,624,635,646],{},[83,625,626,629,632],{},[98,627,628],{},"2026 邊緣 FPGA（LPDDR5）",[98,630,631],{},"25 GB\u002Fs",[98,633,634],{},"約 4 tok\u002Fs",[83,636,637,640,643],{},[98,638,639],{},"2030 3D FPGA（3D DRAM）",[98,641,642],{},"2 TB\u002Fs",[98,644,645],{},"約 340 tok\u002Fs",[83,647,648,651,654],{},[98,649,650],{},"2030 GPU（HBM4）",[98,652,653],{},"8 TB\u002Fs",[98,655,656],{},"約 1,370 tok\u002Fs",[15,658,659],{},"從 4 到 340 是 85 倍。這 85 倍跨了兩個產品級別，不能直接當成「同級比較」。",[15,661,662],{},"跟同年的 GPU 比，3D FPGA 仍然慢約四倍。但這個比較只在「大模型、批次、頻寬受限」時才決定勝負。在延遲敏感、模型碎片化、每瓦 token 被寫進規格書的場景，基準換了，答案也會換。",[15,664,665],{},"相對 2026 年同級 FPGA，我們的推估分佈是：",[77,667,668,681],{},[80,669,670],{},[83,671,672,675,678],{},[86,673,674],{},"倍數",[86,676,677],{},"機率",[86,679,680],{},"情境",[93,682,683,694,705,716,727],{},[83,684,685,688,691],{},[98,686,687],{},"\u003C3×",[98,689,690],{},"15%",[98,692,693],{},"只做到 2-tier 邏輯，記憶體照舊",[83,695,696,699,702],{},[98,697,698],{},"3–10×",[98,700,701],{},"25%",[98,703,704],{},"3D DRAM 到位，編譯器仍弱",[83,706,707,710,713],{},[98,708,709],{},"10–30×",[98,711,712],{},"35%",[98,714,715],{},"邏輯、記憶體、工具鏈三者同時到位",[83,717,718,721,724],{},[98,719,720],{},"30–80×",[98,722,723],{},"20%",[98,725,726],{},"窄門：3B 以下模型、全 SRAM、邊緣對邊緣",[83,728,729,732,735],{},[98,730,731],{},">80×",[98,733,734],{},"5%",[98,736,737],{},"需要 CIM 或類比，或者基準作弊",[15,739,740],{},"中位數大約 15 倍，期望值大約 22 倍。這組數字偏樂觀，理由是麒麟已經把密度與功耗同時做出來。那是三把鑰匙裡最難的一把。",[19,742,743],{"id":743},"我的判斷",[77,745,746,755],{},[80,747,748],{},[83,749,750,753],{},[86,751,752],{},"情境（未來 5 年）",[86,754,677],{},[93,756,757,765,773,781,788],{},[83,758,759,762],{},[98,760,761],{},"折疊成為某一家 FPGA 旗艦的標準微架構",[98,763,764],{},"60%",[83,766,767,770],{},[98,768,769],{},"中國 3D 路線在 AI 加速器落地（昇騰 990 如期）",[98,771,772],{},"65%",[83,774,775,778],{},[98,776,777],{},"FPGA／CGRA 在邊緣推論拿下可觀市佔",[98,779,780],{},"40%",[83,782,783,786],{},[98,784,785],{},"出現以折疊為核心賣點、年營收逾 10 億美元的新公司",[98,787,690],{},[83,789,790,793],{},[98,791,792],{},"折疊讓 FPGA 在資料中心推論取代 GPU 的一部分",[98,794,795],{},"10%",[15,797,798],{},"這些是判斷，不是預測模型。它們的共同前提是：工具鏈要在 2028 年前追上硬體。追不上，上面全部往下修。",[19,800,801],{"id":801},"這篇的限制",[15,803,804,807],{},[32,805,806],{},"一、我們沒有實測。"," 所有數字來自公開報導、論文與廠商說法；麒麟那組功耗數字是華為自行量測。",[15,809,810,813],{},[32,811,812],{},"二、樂觀有來源，也有偏誤。"," 麒麟是個案，而且是華為在特定條件下（選擇性折疊、手機功耗預算）調出來的結果。換到 600mm² 的 FPGA，散熱與良率的帳要重算。",[15,815,816,819],{},[32,817,818],{},"三、機率是判斷。"," 沒有統計模型，請當成「我們的看法」。",[15,821,822,825],{},[32,823,824],{},"四、未來的推估建立在三個假設上。"," 混合鍵合的良率與成本在 2030 年前達標、3D-aware 工具鏈成熟、2030 年的 GPU 沒有進步得比預期快。",[19,827,828],{"id":828},"如果你要下注",[15,830,831,832,836],{},"三個問題，比記住任何數字有用。這是我們做",[148,833,835],{"href":834},"\u002Fservices","概念驗證","時的前三題。",[15,838,839,842],{},[32,840,841],{},"一、你的模型還會不會變？"," 會變，可重構的價值就成立；已經定型、出貨量又大，去開 ASIC。",[15,844,845,848],{},[32,846,847],{},"二、你的瓶頸是頻寬還是延遲？"," 大模型批次推論，頻寬決定一切，FPGA 不會贏；延遲、離線、每瓦 token，這些是它的地盤。",[15,850,851,854],{},[32,852,853],{},"三、你的比較基準是 die，還是板子？"," 只要競品是「2–4 顆離散元件加一塊板子」，折疊就有帳可算。",[15,856,857],{},"至於要不要現在押注——我們的經驗是，硬體路線的賭注通常輸在「太早下注」，而不是「太晚跟上」。但這一次，值得把它放進 2027 年的選項清單裡。",{"title":859,"searchDepth":860,"depth":860,"links":861},"",2,[862,863,864,865,866,867,868,869,870,871,872],{"id":21,"depth":860,"text":21},{"id":40,"depth":860,"text":41},{"id":72,"depth":860,"text":72},{"id":198,"depth":860,"text":199},{"id":256,"depth":860,"text":257},{"id":294,"depth":860,"text":295},{"id":334,"depth":860,"text":335},{"id":392,"depth":860,"text":393},{"id":743,"depth":860,"text":743},{"id":801,"depth":860,"text":801},{"id":828,"depth":860,"text":828},"\u002Fimages\u002Fblog\u002Flogic-folding-fpga-cgra.svg","邏輯折疊把邏輯區塊拆成上下兩層堆疊的示意圖","2026-10-25","麒麟 2026 已經把邏輯折疊帶進量產，密度 +55%、同效能功耗大降。同一個槓桿，能不能把 FPGA／CGRA 從二十年的死胡同裡拉出來？這篇看它解鎖什麼、還缺什麼、以及 2030 年前要盯哪些檢查點。",false,"md","zh-TW",{},true,"\u002Fimages\u002Fblog\u002Flogic-folding-fpga-cgra.jpg","\u002Fblog\u002Fzh-tw\u002Flogic-folding-fpga-cgra",{"title":6,"description":876},"logic-folding-fpga-cgra","blog\u002Fzh-TW\u002Flogic-folding-fpga-cgra",[888,889,890],"fpga","cgra","hardware",null,"ZLO0bnOuzLOnC9C4wZH-KP3lBPxf7NcvEuwfvwTfbhc",{"id":894,"title":895,"author":7,"body":896,"cover":1663,"coverAlt":1664,"date":875,"description":1665,"draft":877,"extension":878,"featured":877,"lang":1666,"meta":1667,"navigation":881,"ogImage":1668,"path":1669,"seo":1670,"slug":885,"stem":1671,"tags":1672,"translationKey":885,"updated":891,"__hash__":1673},"blog\u002Fblog\u002Fen\u002Flogic-folding-fpga-cgra.md","An exit from the FPGA dead end",{"type":9,"value":897,"toc":1650},[898,903,907,910,913,919,922,926,929,949,952,956,959,1012,1015,1050,1058,1061,1065,1068,1084,1095,1105,1116,1120,1123,1129,1135,1141,1147,1154,1158,1161,1167,1173,1179,1190,1193,1197,1251,1255,1258,1412,1415,1462,1465,1468,1471,1533,1536,1540,1588,1591,1595,1601,1607,1613,1619,1623,1629,1635,1641,1647],[12,899,900],{},[15,901,902],{},"No benchmarks of our own here. Facts that have happened are linked. Forecasts and probabilities are our judgment, and we label them. We are optimistic about this direction, and we write down what would have to be true for it to hold.",[19,904,906],{"id":905},"the-short-answer","The short answer",[15,908,909],{},"In September 2026, the Kirin 2026 shipped. It is the first SoC in volume production with logic folding, and after teardown the numbers are: density up from 155 to 238 MTr\u002Fmm² (+55%), and at equal performance, NPU power down 66% and the CPU prime core down 41%.",[15,911,912],{},"This is not a roadmap. It is a phone chip already in people's hands.",[15,914,915,916],{},"So the real question is not whether Huawei can do it. It is: ",[32,917,918],{},"can the same lever pull FPGA and CGRA out of a twenty-year dead end?",[15,920,921],{},"Our answer: it looks promising. Not because the numbers got bigger, but because it loosens three constraints at once — and those three are exactly where AI hurts most.",[19,923,925],{"id":924},"the-dead-end-what-the-fpga-is-stuck-on","The dead end: what the FPGA is stuck on",[15,927,928],{},"The FPGA is not weak. Three structural problems keep it at glue and prototypes:",[46,930,931,937,943],{},[49,932,933,936],{},[32,934,935],{},"Area."," Configuration SRAM and programmable switches eat a large share of the die. The same function is an order of magnitude bigger than in an ASIC.",[49,938,939,942],{},[32,940,941],{},"The memory wall."," Programmable fabric cannot reach HBM-class bandwidth, so it hangs off external DRAM. Once inference moves to large models, it loses on data movement first.",[49,944,945,948],{},[32,946,947],{},"Staticity."," Weights and routing are fixed at synthesis time. Change the model and you run the whole toolchain again. In an era when models are revised every quarter, that is the largest cost of all.",[15,950,951],{},"The third is discussed least, and it is where the FPGA should be winning in AI. The hardware just was never fast or cheap enough to change.",[19,953,955],{"id":954},"folding-hands-over-three-keys","Folding hands over three keys",[15,957,958],{},"In 2026, logic folding means two different things, and they unlock different locks:",[77,960,961,971],{},[80,962,963],{},[83,964,965,968],{},[86,966,967],{},"Huawei LogicFolding (folds Z)",[86,969,970],{},"Academic temporal logic folding (folds T)",[93,972,973,986,999],{},[83,974,975,981],{},[98,976,977,980],{},[32,978,979],{},"How:"," one logic block split across two dies, bonded face to face",[98,982,983,985],{},[32,984,979],{}," the same LUTs reconfigured every few cycles",[83,987,988,994],{},[98,989,990,993],{},[32,991,992],{},"Unlocks:"," density, frequency, shorter paths",[98,995,996,998],{},[32,997,992],{}," area out of time; reconfiguration as the norm",[83,1000,1001,1007],{},[98,1002,1003,1006],{},[32,1004,1005],{},"Evidence:"," Kirin 2026 (in production)",[98,1008,1009,1011],{},[32,1010,1005],{}," NATURE\u002FNanoMap, Tabula Spacetime",[15,1013,1014],{},"The three keys map onto the three problems:",[139,1016,1017,1028,1039],{},[49,1018,1019,1022,1023,1027],{},[32,1020,1021],{},"Density."," Move configuration memory out of the logic layer (",[148,1024,1026],{"href":150,"rel":1025},[152],"M3D FPGA, DAC 2025",") and the area tax finally gets a discount.",[49,1029,1030,1033,1034,1038],{},[32,1031,1032],{},"Bandwidth."," Bond SRAM or DRAM on top. A 28nm 3D logic-on-SRAM CGRA has already shown ",[148,1035,1037],{"href":163,"rel":1036},[152],"4TB\u002Fs of vertical bandwidth",", on 51.19mm² at 1GHz and 0.9V.",[49,1040,1041,1044,1045,1049],{},[32,1042,1043],{},"Reconfiguration speed."," Hybrid bonding brings reprogramming latency below 10ns (",[148,1046,1048],{"href":180,"rel":1047},[152],"vFPGA, 2026","). Temporal folding becomes affordable for the first time.",[15,1051,1052,1053,1057],{},"One more: face-to-face bonding shortens wires. ",[148,1054,1056],{"href":189,"rel":1055},[152],"LaZagna (ICCAD 2025)"," measured up to 6.7% critical path reduction and 22.9% less wirelength in VTR simulation.",[15,1059,1060],{},"None of these is a revolution on its own. Together, they are the first chance in twenty years to push all three taxes down at the same time.",[19,1062,1064],{"id":1063},"what-has-already-happened-not-what-is-forecast","What has already happened, not what is forecast",[15,1066,1067],{},"Everything in this section is checkable. That matters, because it moves folding from papers to products.",[15,1069,1070,1073,1074,1078,1079,1083],{},[32,1071,1072],{},"Density and power."," Against the previous planar Kirin 9030 Pro: +55% density, and at equal performance NPU power down 66% and the CPU prime core down 41%, with ",[148,1075,1077],{"href":211,"rel":1076},[152],"GPU figures reported between 45% and 58%",". ",[148,1080,1082],{"href":216,"rel":1081},[152],"Huawei's explanation",": most of a chip's energy goes into moving data along metal wires. Folding shortens those wires and cuts interconnect capacitance, so equal performance can be had at lower frequency and voltage.",[15,1085,1086,1089,1090,1094],{},[32,1087,1088],{},"More surgical than expected."," Huawei calls it selective folding: only critical paths and critical timing get folded. Thermal-aware placement interleaves hot and cool circuits so hotspots do not stack vertically. Vertical interconnects already exceed 100 million, with a ",[148,1091,1093],{"href":211,"rel":1092},[152],"three-year target of 720nm top-metal pitch and over 200 million interconnects",".",[15,1096,1097,1100,1101,1104],{},[32,1098,1099],{},"Process is no longer the excuse."," SMIC's N+3 has entered 5nm-class volume production (",[148,1102,240],{"href":238,"rel":1103},[152],"). Folding is not a substitute for missing process technology, then, but an architectural option worth taking even when the process is there. That changes the nature of the argument.",[15,1106,1107,1110,1111,1115],{},[32,1108,1109],{},"The official roadmap puts it in AI accelerators."," Per the V2 Tau paper, Ascend 910C in 2025 and 950 in 2026 still use chiplets and 2.5D; ",[148,1112,1114],{"href":250,"rel":1113},[152],"around 2030, Ascend 990 brings logic folding into AI accelerators",", and from then on 3D folding carries the main line.",[19,1117,1119],{"id":1118},"looking-forward-what-folding-actually-unlocks","Looking forward: what folding actually unlocks",[15,1121,1122],{},"If folding holds up, the FPGA's role in inference moves from glue to reconfigurable inference engine. Four things become practical:",[15,1124,1125,1128],{},[32,1126,1127],{},"One: continual learning."," Weights and routing update with the data, without taping out for every model version. This is the ASIC's structural weakness: change the model and it is obsolete.",[15,1130,1131,1134],{},[32,1132,1133],{},"Two: dynamic routing."," MoE expert routing is, at heart, \"each token takes a different path\". Making that reconfigurable in hardware is cheaper than simulating it with caches in software. Routing is what FPGAs and CGRAs already do.",[15,1136,1137,1140],{},[32,1138,1139],{},"Three: dynamic weights and precision."," One chip can run INT4 today and FP8 tomorrow, or change where KV lives when the context gets long. GPUs schedule this in software; reconfigurable hardware can change the circuit.",[15,1142,1143,1146],{},[32,1144,1145],{},"Four: edge and field."," Sites that cannot reach the network, cannot afford a loud fan, cannot risk a supply cut — they need something buyable, changeable and supported for ten years. GPUs cannot go there and ASIC volumes cannot sustain it.",[15,1148,1149,1150,1153],{},"Put those together and the conclusion is different from the usual one: ",[32,1151,1152],{},"the FPGA does not sell compute. It sells the ability to face uncertainty."," And the next stretch of AI is full of it.",[19,1155,1157],{"id":1156},"careful-though-four-things-still-missing","Careful, though: four things still missing",[15,1159,1160],{},"Optimism is not blindness. If these four are not solved, folding stays a nice prototype.",[15,1162,1163,1166],{},[32,1164,1165],{},"One: the 2026 implementation is conservative."," Kirin uses micro-bumps and standard-pitch bonding, not the finest pitch, and TSV keep-out zones still displace standard cells. The real density dividend waits for finer pitch.",[15,1168,1169,1172],{},[32,1170,1171],{},"Two: the toolchain."," 3D demands cross-die place-and-route, timing, thermal and signal-integrity signoff, with all stacked dies treated as one continuous design entity. For an FPGA that means rewriting the whole compile flow. This is harder than bonding wafers.",[15,1174,1175,1178],{},[32,1176,1177],{},"Three: heat and yield."," Two active logic layers double power density. Huawei proved with a phone that \"denser does not mean hotter\", but FPGAs live in fanless, industrial and base-station environments where the test is ten-year reliability, not a benchmark.",[15,1180,1181,1184,1185,1189],{},[32,1182,1183],{},"Four: cost."," Even HBM4 is still ",[148,1186,1188],{"href":325,"rel":1187},[152],"hesitating"," on hybrid bonding. Yields multiply, costs add, and nobody has said who pays the premium.",[15,1191,1192],{},"These are not reasons to dismiss it. They are the list of what \"it works\" would have to mean.",[19,1194,1196],{"id":1195},"checkpoints-what-to-watch-over-the-next-three-years","Checkpoints: what to watch over the next three years",[77,1198,1199,1209],{},[80,1200,1201],{},[83,1202,1203,1206],{},[86,1204,1205],{},"Signal",[86,1207,1208],{},"Why it matters",[93,1210,1211,1219,1227,1235,1243],{},[83,1212,1213,1216],{},[98,1214,1215],{},"Bonding pitch below 720nm, interconnects past 200 million",[98,1217,1218],{},"Whether the density dividend continues",[83,1220,1221,1224],{},[98,1222,1223],{},"Ascend 990 ships folding before 2030",[98,1225,1226],{},"Real adoption in AI accelerators, not just phones",[83,1228,1229,1232],{},[98,1230,1231],{},"A commercial 3D logic-on-logic FPGA",[98,1233,1234],{},"From \"Huawei's SoC\" to \"the industry's option\"",[83,1236,1237,1240],{},[98,1238,1239],{},"3D-aware EDA and compilers push utilisation up",[98,1241,1242],{},"Without tools, the hardware is a sample",[83,1244,1245,1248],{},[98,1246,1247],{},"Edge tokens\u002FJ clearly ahead of a 2026 GPU",[98,1249,1250],{},"Commercial value has to land on inference per watt",[19,1252,1254],{"id":1253},"the-optimistic-2030-case","The optimistic 2030 case",[15,1256,1257],{},"Decode speed follows one relation:",[398,1259,1261],{"className":1260},[401],[398,1262,1264,1296],{"className":1263},[405],[398,1265,1267],{"className":1266},[409],[411,1268,1269],{"xmlns":413,"display":414},[416,1270,1271,1293],{},[419,1272,1273,1276,1278],{},[422,1274,1275],{},"tokens\u002Fs",[426,1277,428],{},[430,1279,1280,1290],{},[419,1281,1282,1285,1287],{},[422,1283,1284],{},"memory bandwidth",[426,1286,439],{},[422,1288,1289],{},"efficiency",[422,1291,1292],{},"bytes of weights read per token",[447,1294,1295],{"encoding":449},"\\text{tokens\u002Fs} \\approx \\frac{\\text{memory bandwidth} \\times \\text{efficiency}}{\\text{bytes of weights read per token}}",[398,1297,1299,1320],{"className":1298,"ariaHidden":455},[454],[398,1300,1302,1305,1311,1314,1317],{"className":1301},[459],[398,1303],{"className":1304,"style":464},[463],[398,1306,1308],{"className":1307},[468,469],[398,1309,1275],{"className":1310},[468],[398,1312],{"className":1313,"style":477},[476],[398,1315,428],{"className":1316},[481],[398,1318],{"className":1319,"style":477},[476],[398,1321,1323,1327],{"className":1322},[459],[398,1324],{"className":1325,"style":1326},[463],"height:2.2519em;vertical-align:-0.8804em;",[398,1328,1330,1333,1409],{"className":1329},[468],[398,1331],{"className":1332},[498,499],[398,1334,1336],{"className":1335},[430],[398,1337,1339,1400],{"className":1338},[506,507],[398,1340,1342,1397],{"className":1341},[511],[398,1343,1346,1360,1368],{"className":1344,"style":1345},[515],"height:1.3714em;",[398,1347,1348,1351],{"style":519},[398,1349],{"className":1350,"style":524},[523],[398,1352,1354],{"className":1353},[468],[398,1355,1357],{"className":1356},[468,469],[398,1358,1292],{"className":1359},[468],[398,1361,1362,1365],{"style":546},[398,1363],{"className":1364,"style":524},[523],[398,1366],{"className":1367,"style":554},[553],[398,1369,1370,1373],{"style":557},[398,1371],{"className":1372,"style":524},[523],[398,1374,1376,1382,1385,1388,1391],{"className":1375},[468],[398,1377,1379],{"className":1378},[468,469],[398,1380,1284],{"className":1381},[468],[398,1383],{"className":1384,"style":573},[476],[398,1386,439],{"className":1387},[577],[398,1389],{"className":1390,"style":573},[476],[398,1392,1394],{"className":1393},[468,469],[398,1395,1289],{"className":1396},[468],[398,1398,591],{"className":1399},[590],[398,1401,1403],{"className":1402},[511],[398,1404,1407],{"className":1405,"style":1406},[515],"height:0.8804em;",[398,1408],{},[398,1410],{"className":1411},[604,499],[15,1413,1414],{},"For a 7B model at INT4, batch 1, efficiency 0.6 (weights about 3.5 GB):",[77,1416,1417,1430],{},[80,1418,1419],{},[83,1420,1421,1424,1427],{},[86,1422,1423],{},"Machine",[86,1425,1426],{},"Bandwidth",[86,1428,1429],{},"Tokens\u002Fs",[93,1431,1432,1442,1452],{},[83,1433,1434,1437,1439],{},[98,1435,1436],{},"2026 edge FPGA (LPDDR5)",[98,1438,631],{},[98,1440,1441],{},"≈ 4",[83,1443,1444,1447,1449],{},[98,1445,1446],{},"2030 3D FPGA (3D DRAM)",[98,1448,642],{},[98,1450,1451],{},"≈ 340",[83,1453,1454,1457,1459],{},[98,1455,1456],{},"2030 GPU (HBM4)",[98,1458,653],{},[98,1460,1461],{},"≈ 1,370",[15,1463,1464],{},"Four to 340 is 85×. That 85× crosses two product classes and is not a like-for-like comparison.",[15,1466,1467],{},"Against a GPU of the same year, the 3D FPGA is still about four times slower. But that comparison only decides the outcome for large models, batched, bandwidth-bound. For latency-sensitive, fragmented, tokens-per-watt-constrained work, the baseline changes and so does the answer.",[15,1469,1470],{},"Relative to a comparable 2026 FPGA, our estimate is:",[77,1472,1473,1486],{},[80,1474,1475],{},[83,1476,1477,1480,1483],{},[86,1478,1479],{},"Multiplier",[86,1481,1482],{},"Probability",[86,1484,1485],{},"Scenario",[93,1487,1488,1497,1506,1515,1524],{},[83,1489,1490,1492,1494],{},[98,1491,687],{},[98,1493,690],{},[98,1495,1496],{},"Two-tier logic only, memory unchanged",[83,1498,1499,1501,1503],{},[98,1500,698],{},[98,1502,701],{},[98,1504,1505],{},"3D DRAM arrives, compilers stay weak",[83,1507,1508,1510,1512],{},[98,1509,709],{},[98,1511,712],{},[98,1513,1514],{},"Logic, memory and toolchain all land together",[83,1516,1517,1519,1521],{},[98,1518,720],{},[98,1520,723],{},[98,1522,1523],{},"Narrow gate: ≤3B models, all-SRAM, edge to edge",[83,1525,1526,1528,1530],{},[98,1527,731],{},[98,1529,734],{},[98,1531,1532],{},"Requires compute-in-memory or analog — or a rigged baseline",[15,1534,1535],{},"Median around 15×, expectation around 22×. These numbers are more optimistic than our earlier version, because Kirin already delivered density and power at the same time. That was the hardest of the three keys.",[19,1537,1539],{"id":1538},"our-read","Our read",[77,1541,1542,1551],{},[80,1543,1544],{},[83,1545,1546,1549],{},[86,1547,1548],{},"Scenario over five years",[86,1550,1482],{},[93,1552,1553,1560,1567,1574,1581],{},[83,1554,1555,1558],{},[98,1556,1557],{},"Folding becomes the standard microarchitecture of at least one flagship FPGA",[98,1559,764],{},[83,1561,1562,1565],{},[98,1563,1564],{},"China's 3D path lands in AI accelerators (Ascend 990 on schedule)",[98,1566,772],{},[83,1568,1569,1572],{},[98,1570,1571],{},"FPGA\u002FCGRA takes meaningful share of edge inference",[98,1573,780],{},[83,1575,1576,1579],{},[98,1577,1578],{},"A new company built around folding reaches $1B annual revenue",[98,1580,690],{},[83,1582,1583,1586],{},[98,1584,1585],{},"Folding lets FPGAs take part of data-center inference from GPUs",[98,1587,795],{},[15,1589,1590],{},"These are judgments, not a model. Their common premise is that toolchains catch up with hardware by 2028. If they do not, everything above comes down.",[19,1592,1594],{"id":1593},"limits","Limits",[15,1596,1597,1600],{},[32,1598,1599],{},"We have no measurements."," Every number comes from public reporting, papers or vendors; the Kirin power figures are Huawei's own measurements.",[15,1602,1603,1606],{},[32,1604,1605],{},"The optimism has a source, and a bias."," Kirin is one data point, tuned under phone power budgets and selective folding. Move to a 600mm² FPGA and the heat and yield arithmetic has to be redone.",[15,1608,1609,1612],{},[32,1610,1611],{},"The probabilities are ours."," No statistical model stands behind them. Treat them as a view.",[15,1614,1615,1618],{},[32,1616,1617],{},"The forecast rests on three assumptions."," Hybrid bonding yield and cost land by 2030, 3D-aware toolchains mature, and 2030 GPUs do not improve faster than expected.",[19,1620,1622],{"id":1621},"if-youre-placing-a-bet","If you're placing a bet",[15,1624,1625,1626,1094],{},"Three questions beat memorising any number here. They are also the first three we ask in a ",[148,1627,1628],{"href":834},"proof of concept",[15,1630,1631,1634],{},[32,1632,1633],{},"Will your model keep changing?"," If yes, reconfigurable value holds. If it is settled and volumes are large, tape out an ASIC.",[15,1636,1637,1640],{},[32,1638,1639],{},"Is your bottleneck bandwidth or latency?"," For large-model batched inference, bandwidth decides and the FPGA does not win. Latency, offline, tokens per watt — that is its ground.",[15,1642,1643,1646],{},[32,1644,1645],{},"Is your baseline a die or a board?"," If you compete against 2–4 discrete parts and a PCB, folding has an account to settle.",[15,1648,1649],{},"As for betting now: hardware bets are usually lost to being early, not to being late. But this one is worth putting on the 2027 options list.",{"title":859,"searchDepth":860,"depth":860,"links":1651},[1652,1653,1654,1655,1656,1657,1658,1659,1660,1661,1662],{"id":905,"depth":860,"text":906},{"id":924,"depth":860,"text":925},{"id":954,"depth":860,"text":955},{"id":1063,"depth":860,"text":1064},{"id":1118,"depth":860,"text":1119},{"id":1156,"depth":860,"text":1157},{"id":1195,"depth":860,"text":1196},{"id":1253,"depth":860,"text":1254},{"id":1538,"depth":860,"text":1539},{"id":1593,"depth":860,"text":1594},{"id":1621,"depth":860,"text":1622},"\u002Fimages\u002Fblog\u002Fen\u002Flogic-folding-fpga-cgra.svg","A logic block split across two stacked dies, bonded face to face","Kirin 2026 already ships logic folding: +55% density, much lower power. Can the same lever pull FPGA and CGRA out of a twenty-year dead end? What it unlocks, what is missing, and what to watch.","en",{},"\u002Fimages\u002Fblog\u002Fen\u002Flogic-folding-fpga-cgra.jpg","\u002Fblog\u002Fen\u002Flogic-folding-fpga-cgra",{"title":895,"description":1665},"blog\u002Fen\u002Flogic-folding-fpga-cgra",[888,889,890],"jlWz0UYPuCakec4aqQT3zgpiWnPWq3FLZBFIh6JXeU8",{"id":1675,"company":1676,"extension":1687,"meta":1688,"services":1689,"social":1767,"stem":1768,"__hash__":1769},"site\u002Fsite.yml",{"name":1677,"nameEn":1678,"email":1679,"address":1680,"addressEn":1681,"lineUrl":1682,"lineId":1683,"duns":1684,"youtube":1685,"youtubeId":1686},"銡策數位有限公司","Jecision Digital Co., Ltd.","contact@jecision.com","231 新北市新店區北新路二段 262 號 3 樓之 3","3F.-3, No. 262, Sec. 2, Beixin Rd., Xindian Dist., New Taipei City 231, Taiwan","https:\u002F\u002Fline.me\u002FR\u002Fti\u002Fp\u002F@374qnumi","@374qnumi","963905705","https:\u002F\u002Fwww.youtube.com\u002Fshorts\u002F6UE0WTmyjsg","6UE0WTmyjsg","yml",{},[1690,1714,1740],{"key":1691,"zh":1692,"en":1703},"audit",{"title":1693,"tagline":1694,"summary":1695,"points":1696,"deliverable":1700,"detail":1701,"duration":1702},"企業 AI 導入健檢","先看清楚，再花錢","60 分鐘線上訪談，盤點最耗時、最依賴人力的營運環節；我們會告訴你哪些工作現在就能交給 AI、哪些還不成熟。",[1697,1698,1699],"現況盤點：梳理日常營運中最耗時、最依賴人力的環節","痛點診斷：判斷哪些工作現在就能交給 AI，哪些建議先保留人力","可行性評估：依你的業務特性與預算，篩選適合的模型與工具","《企業 AI 導入建議報告書》（PDF）","含 1–2 個「開發成本最低、成效最明顯」的優先項目、技術棧建議、預期節省的人力時間與下一步","訪談 60 分鐘，報告書 3 個工作天內交付",{"title":1704,"tagline":1705,"summary":1706,"points":1707,"deliverable":1711,"detail":1712,"duration":1713},"AI Readiness Audit","Look before you spend","A 60-minute remote audit of the workflows that eat the most time and people-power — and an honest answer on what AI can take over today, and what it cannot.",[1708,1709,1710],"Audit the daily workflows that consume the most time and headcount","Triage which tasks AI can own today, and which should stay human","Shortlist the models and tools that fit your budget and constraints","AI Adoption Recommendation Report (PDF)","One or two highest-ROI entry points, a recommended tech stack, expected hours saved, and the concrete next step","60-minute call, report delivered within 3 business days",{"key":1715,"zh":1716,"en":1727},"prompt",{"title":1717,"tagline":1718,"summary":1719,"points":1720,"deliverable":1724,"detail":1725,"duration":1726},"提示詞工程","讓 AI 穩定產出，而不是碰運氣","針對你的實際任務設計提示詞與多步驟工作流，並做極限測試，確保換了資料、換了人操作也不會走鐘。",[1721,1722,1723],"客製提示詞：ChatGPT、Claude、Gemini、Midjourney 等主流工具的專屬模板","除錯與優化：修掉幻覺、格式跑掉、時好時壞的問題","工作流建置：把複雜任務拆成多步驟提示詞與可重複的 SOP","提示詞文件或設定檔","附使用說明與範例，並提供 1 對 1 教學，確保你與團隊能自己維護","依任務複雜度報價，通常 3–7 個工作天",{"title":1728,"tagline":1729,"summary":1730,"points":1731,"deliverable":1737,"detail":1738,"duration":1739},"Prompt Engineering","Make AI produce reliably, not by luck","Prompt sets and multi-step workflows designed for your actual tasks, stress-tested so they keep working when the data or the operator changes.",[1732,1733,1735],"Custom prompts for ChatGPT, Claude, Gemini, Midjourney and friends",{"Debugging and tuning":1734},"kill hallucinations, broken formats and flaky output",{"Workflow design":1736},"break complex work into repeatable multi-step SOPs","Prompt library or exportable config","Ships with usage notes and examples, plus a 1:1 walkthrough so your team can maintain it","Quoted by complexity, typically 3–7 business days",{"key":1741,"zh":1742,"en":1753},"poc",{"title":1743,"tagline":1744,"summary":1745,"points":1746,"deliverable":1750,"detail":1751,"duration":1752},"極速 PoC","五天，看到能跑的東西","不談架構藍圖，直接做一個能動的雛形。五個工作天內交付線上可操作的智能體，用你真實的資料驗證。",[1747,1748,1749],"Day 1：15 分鐘對焦，鎖定單一痛點與資料盤點","Day 2–4：模型串接、邏輯設計與雛形開發","Day 5：Demo 展示與 AI 擴展建議書","可線上操作的智能體雛形","交付範圍為概念驗證與展示，不含後續維運或大規模伺服器部署；要進階成完整系統會另行報價","5 個工作天",{"title":1754,"tagline":1755,"summary":1756,"points":1757,"deliverable":1764,"detail":1765,"duration":1766},"Rapid PoC","Five days to something that runs","No architecture decks — a working prototype built in five business days, validated against your real data.",[1758,1760,1762],{"Day 1":1759},"15-minute scoping call, one pain point, data inventory",{"Day 2–4":1761},"model integration, logic design, prototype build",{"Day 5":1763},"live demo plus an AI expansion recommendation","A runnable online agent prototype","Proof of concept and demo scope only; ongoing operations and large-scale deployment are quoted separately","5 business days",[],"site","XTwARfVAOcrXNiKehsM6V6cdkd2HXy4d5yZVrSWrI3Q",[1771,1986],{"id":1772,"title":1773,"author":7,"body":1774,"cover":1971,"coverAlt":1972,"date":1973,"description":1974,"draft":877,"extension":878,"featured":881,"lang":1666,"meta":1975,"navigation":881,"ogImage":1976,"path":1977,"seo":1978,"slug":1979,"stem":1980,"tags":1981,"translationKey":1979,"updated":891,"__hash__":1985},"blog\u002Fblog\u002Fen\u002Fhello-jecision.md","Moving the blog off a domain nobody could find",{"type":9,"value":1775,"toc":1963},[1776,1780,1783,1803,1809,1813,1816,1831,1839,1843,1864,1882,1888,1892,1898,1908,1921,1925,1950,1954,1960],[19,1777,1779],{"id":1778},"it-started-with-one-line-of-source-code","It started with one line of source code",[15,1781,1782],{},"I was sending an old article to a colleague, so I grabbed the page source, and stopped.",[15,1784,1785,1786,1790,1791,1794,1795,1798,1799,1802],{},"No ",[1787,1788,1789],"code",{},"lang"," on ",[1787,1792,1793],{},"\u003Chtml>",". No ",[1787,1796,1797],{},"\u003Ctitle>",". No description, no Open Graph, no canonical, not a single line of JSON-LD. The math was worse: the source contained the literal string ",[1787,1800,1801],{},"\\operatorname{Attention}",", and only became typeset once JavaScript finished running.",[15,1804,1805,1806],{},"Which means: ",[32,1807,1808],{},"to a search engine, that article never existed.",[19,1810,1812],{"id":1811},"how-it-got-that-way","How it got that way",[15,1814,1815],{},"Not carelessness — we used the tool harder than it was designed to be used.",[15,1817,1818,1819,1822,1823,1826,1827,1830],{},"To make formulas render, we wrapped LaTeX in ",[1787,1820,1821],{},"\u003Cdiv class=\"latex-block\">"," and replaced its ",[1787,1824,1825],{},"textContent"," with KaTeX output inside ",[1787,1828,1829],{},"onMounted",". It looked perfect in the browser, so nobody questioned it.",[15,1832,1833,1834,1838],{},"The problem is that this couples two things: the content only exists after JavaScript runs, while SEO needs content that exists ",[1835,1836,1837],"em",{},"before"," it does.",[19,1840,1842],{"id":1841},"three-decisions","Three decisions",[15,1844,1845,1848,1849,1852,1853,1856,1857,1852,1860,1863],{},[32,1846,1847],{},"Move the content, not the layout."," All 12 articles were converted to ",[1787,1850,1851],{},"$...$"," and ",[1787,1854,1855],{},"$$...$$",", handled by ",[1787,1858,1859],{},"remark-math",[1787,1861,1862],{},"rehype-katex"," at build time. Math is now part of the HTML.",[15,1865,1866,1869,1870,1873,1874,1877,1878,1881],{},[32,1867,1868],{},"Let data decide the URL, not the filename."," The old filenames looked like ",[1787,1871,1872],{},"2604.04921v1.md",", and the resulting URL was ",[1787,1875,1876],{},"\u002Fen\u002Fblog\u002F04921v1"," — the numeric prefix silently vanished. Now a ",[1787,1879,1880],{},"slug"," field in frontmatter owns the URL.",[15,1883,1884,1887],{},[32,1885,1886],{},"Not a single old URL may break."," 28 redirects, including trailing-slash variants.",[19,1889,1891],{"id":1890},"three-bugs-that-almost-broke-the-launch","Three bugs that almost broke the launch",[15,1893,1894,1897],{},[32,1895,1896],{},"The eaten slug."," Discovered by fetching the live page, not by reading the code. Had we skipped that, we would have assumed a move is just copying files.",[15,1899,1900,1903,1904,1907],{},[32,1901,1902],{},"hreflang pointing at 404s."," The i18n module generates alternates for every locale, but a Chinese-only article has no English version. ",[1787,1905,1906],{},"nuxt generate"," failed with \"Article not found, linked from \u002Fblog\u002Fxxx\". The fix was not to disable the check, but to let each page declare which locales actually exist.",[15,1909,1910,1916,1917,1920],{},[32,1911,1912,1915],{},[1787,1913,1914],{},"\u002Fsitemap.xml"," was HTML."," The build succeeded, the file existed, it had content — but it was a ",[1787,1918,1919],{},"\u003Cmeta http-equiv=\"refresh\">"," shim, not XML. Google would reject it outright. A post-build step now writes the sitemap index into that path.",[19,1922,1924],{"id":1923},"where-we-are","Where we are",[139,1926,1927,1930,1937,1944],{},[49,1928,1929],{},"Math is typeset server-side, with MathML in the markup",[49,1931,1932,1933,1936],{},"Every page has title, description, canonical, hreflang, OG; articles carry ",[1787,1934,1935],{},"BlogPosting"," structured data",[49,1938,1939,1940,1943],{},"RSS, ",[1787,1941,1942],{},"llms.txt",", sitemap and redirects all in place",[49,1945,1946,1947,1949],{},"An ",[1787,1948,1691],{}," script checks 25 pages for SEO regressions and broken links on every build: currently 0 errors, 0 warnings",[19,1951,1953],{"id":1952},"the-one-line-takeaway","The one-line takeaway",[15,1955,1956,1957,1094],{},"Most of the work in a migration is not moving things — it is ",[32,1958,1959],{},"proving the things arrived",[15,1961,1962],{},"So we turned \"should be there\" into a check that runs on every build. People forget; scripts do not.",{"title":859,"searchDepth":860,"depth":860,"links":1964},[1965,1966,1967,1968,1969,1970],{"id":1778,"depth":860,"text":1779},{"id":1811,"depth":860,"text":1812},{"id":1841,"depth":860,"text":1842},{"id":1890,"depth":860,"text":1891},{"id":1923,"depth":860,"text":1924},{"id":1952,"depth":860,"text":1953},"\u002Fimages\u002Fblog\u002Fhello-jecision.svg","Diagram of moving from a temporary domain to the brand domain","2026-10-23","The old site shipped every article with no title tag, description or canonical URL — and LaTeX that only appeared after JavaScript ran. Here is the move, and the three bugs that almost broke it.",{},"\u002Fimages\u002Fblog\u002Fhello-jecision.jpg","\u002Fblog\u002Fen\u002Fhello-jecision",{"title":1773,"description":1974},"hello-jecision","blog\u002Fen\u002Fhello-jecision",[1982,1983,1984],"nuxt","seo","refactor","PlVBD_RgdHCXJkT3ukEiEkY-5EE2a1TcCkXiLDn5R7M",{"id":1987,"title":1988,"author":7,"body":1989,"cover":2244,"coverAlt":2245,"date":2246,"description":2247,"draft":877,"extension":878,"featured":877,"lang":1666,"meta":2248,"navigation":881,"ogImage":2249,"path":2250,"seo":2251,"slug":2252,"stem":2253,"tags":2254,"translationKey":2252,"updated":891,"__hash__":2257},"blog\u002Fblog\u002Fen\u002Farxiv-2510-27688v1.md","CALM, or why token-by-token generation hit a wall",{"type":9,"value":1990,"toc":2236},[1991,2006,2010,2013,2016,2030,2033,2037,2044,2051,2100,2105,2109,2115,2121,2126,2137,2140,2145,2159,2163,2180,2184,2205,2209,2216,2219,2233],[15,1992,1993,1996,1997,2000,2001],{},[32,1994,1995],{},"From"," — Tencent WeChat AI × Tsinghua University\n",[32,1998,1999],{},"Paper"," — ",[148,2002,2005],{"href":2003,"rel":2004},"https:\u002F\u002Farxiv.org\u002Fhtml\u002F2510.27688v1",[152],"arXiv:2510.27688",[19,2007,2009],{"id":2008},"the-wall","The wall",[15,2011,2012],{},"Every large language model today predicts one token at a time. Each token costs a full forward pass, so cost grows linearly — and with attention, worse — as sequences get longer.",[15,2014,2015],{},"Text representation has already moved from characters to subwords (BPE), but the discrete representation itself is running out of room:",[139,2017,2018,2024],{},[49,2019,2020,2023],{},[32,2021,2022],{},"Vocabulary inflation",": to cover more meaning, vocabularies grew from 32k to 256k. The final layer's compute and memory cost exploded with them.",[49,2025,2026,2029],{},[32,2027,2028],{},"Low information density",": each discrete token carries roughly 15–18 bits. The model has enormous compute and spends it on the labour-intensive job of predicting one low-information token at a time.",[15,2031,2032],{},"CALM's premise: stop picking from a vocabulary, and predict a point in continuous space instead.",[19,2034,2036],{"id":2035},"the-idea","The idea",[15,2038,2039,2040,2043],{},"An autoencoder compresses ",[32,2041,2042],{},"K discrete tokens into one high-dimensional continuous vector",", so sequence length drops from T to T\u002FK and the number of generation steps drops by the same factor.",[15,2045,2046,2047,2050],{},"It trades more ",[1835,2048,2049],{},"semantic bandwidth"," per step for fewer steps.",[77,2052,2053,2065],{},[80,2054,2055],{},[83,2056,2057,2059,2062],{},[86,2058],{},[86,2060,2061],{},"Discrete",[86,2063,2064],{},"CALM (continuous)",[93,2066,2067,2078,2089],{},[83,2068,2069,2072,2075],{},[98,2070,2071],{},"Scaling",[98,2073,2074],{},"vocabulary grows exponentially",[98,2076,2077],{},"vector dimension grows smoothly",[83,2079,2080,2083,2086],{},[98,2081,2082],{},"Objective",[98,2084,2085],{},"pick one of hundreds of thousands",[98,2087,2088],{},"predict coordinates in a continuous space",[83,2090,2091,2094,2097],{},[98,2092,2093],{},"Sequence",[98,2095,2096],{},"long T",[98,2098,2099],{},"short T\u002FK",[12,2101,2102],{},[15,2103,2104],{},"A useful mental image: conventional generation is searching a warehouse with hundreds of thousands of drawers. CALM draws coordinates.",[19,2106,2108],{"id":2107},"four-pillars","Four pillars",[15,2110,2111,2114],{},[32,2112,2113],{},"1. A high-fidelity autoencoder."," Compresses K tokens into 128+ dimensions at roughly 75M parameters of overhead, with reconstruction accuracy above 99.9%. Without this, everything downstream is garbage.",[15,2116,2117,2120],{},[32,2118,2119],{},"2. An energy-based head, no likelihood."," Instead of softmax over a vocabulary, the model regresses the next target vector directly — a single step, not the dozens or hundreds of denoising iterations a diffusion model needs.",[15,2122,2123],{},[32,2124,2125],{},"3. Three tricks for robustness in continuous space.",[139,2127,2128,2131,2134],{},[49,2129,2130],{},"Variational regularisation, to smooth folds and cliffs in the latent space",[49,2132,2133],{},"KL clipping, to stop dimensions collapsing",[49,2135,2136],{},"Double dropout, for extra noise tolerance",[15,2138,2139],{},"Together they build a smooth, elastic landscape where a small prediction error does not turn into gibberish.",[15,2141,2142],{},[32,2143,2144],{},"4. Evaluation without probabilities.",[139,2146,2147,2153],{},[49,2148,2149,2152],{},[32,2150,2151],{},"BrierLM",": perplexity does not apply when there is no likelihood. CALM uses a Brier score (accuracy minus collision rate) as its yardstick, which correlates strongly and negatively with cross-entropy loss.",[49,2154,2155,2158],{},[32,2156,2157],{},"Black-box temperature",": with no probability denominator to tune, batch size N becomes the temperature knob. Small N is cold and deterministic, large N is hot and diverse. With rejection sampling, it behaves much like conventional temperature.",[19,2160,2162],{"id":2161},"the-loop","The loop",[46,2164,2165,2168,2171,2174,2177],{},[49,2166,2167],{},"Input: discrete tokens",[49,2169,2170],{},"Compress: the encoder turns every K tokens into one vector",[49,2172,2173],{},"Process: the transformer runs attention over a much shorter sequence",[49,2175,2176],{},"Predict: the head emits the next continuous vector in one step",[49,2178,2179],{},"Restore: the decoder expands it back into K tokens",[19,2181,2183],{"id":2182},"results","Results",[139,2185,2186,2189,2195,2202],{},[49,2187,2188],{},"With K=4: training compute down 44%, inference compute down 34%, generation steps from T to T\u002F4",[49,2190,2191,2194],{},[32,2192,2193],{},"Larger but cheaper",": 371M parameters (slightly larger than the baseline) with equal or better quality and less total compute",[49,2196,2197,2198,2201],{},"A new scaling axis: ",[32,2199,2200],{},"information density",". As semantic bandwidth grows, CALM reaches a higher Brier score at lower compute — pushing past the old compute–quality frontier",[49,2203,2204],{},"An unusual training curve: performance climbs sharply after ~200k steps and then overtakes conventional models. Learning continuous structure seems to need a long runway before it pays off",[19,2206,2208],{"id":2207},"my-take","My take",[15,2210,2211,2212,2215],{},"The framing is the contribution: ",[32,2213,2214],{},"the vocabulary was never the point",". Discrete tokens are a compression artifact of text, and once you accept that, predicting a continuous vector is the obvious next move.",[15,2217,2218],{},"Two things to watch before believing it replaces anything:",[46,2220,2221,2227],{},[49,2222,2223,2226],{},[32,2224,2225],{},"Reconstruction fidelity is a hard ceiling."," 99.9% sounds great until you multiply it across a long document.",[49,2228,2229,2232],{},[32,2230,2231],{},"Sampling control moves to a different knob."," Batch-size-as-temperature works, but it means your serving stack has to be redesigned around it.",[15,2234,2235],{},"For deployment on constrained hardware, a 4× reduction in generation steps is the most interesting number here — that is the kind of win that changes what fits on a device.",{"title":859,"searchDepth":860,"depth":860,"links":2237},[2238,2239,2240,2241,2242,2243],{"id":2008,"depth":860,"text":2009},{"id":2035,"depth":860,"text":2036},{"id":2107,"depth":860,"text":2108},{"id":2161,"depth":860,"text":2162},{"id":2182,"depth":860,"text":2183},{"id":2207,"depth":860,"text":2208},"\u002Fimages\u002Fblog\u002F2510.27688v1.webp","Continuous autoregressive language models (CALM)","2026-08-06","CALM compresses K discrete tokens into one continuous vector, cutting generation steps to 1\u002FK. Notes on the autoencoder, the likelihood-free head, and what it actually buys you.",{},"\u002Fimages\u002Fblog\u002F2510.27688v1.jpg","\u002Fblog\u002Fen\u002Farxiv-2510-27688v1",{"title":1988,"description":2247},"arxiv-2510-27688v1","blog\u002Fen\u002Farxiv-2510-27688v1",[2255,2256,1289],"paper","llm","GEuIaBm28C9btO5o2N6R_vSuYxGOnyXdP1gu-uYTp8c",1793018952372]